This is to ensure that the simulator and synthesis tool agree with each other, avoiding critical bugs that can only been discovered through gate-level simulation or even post-silicon tests. A rule of thumb is that any signals in your synthesizable design should be declared as logic (a few exceptions apply, which will be discussed). It can either represent a combinational signal or a sequential signal, since the downstream tools such simulator and synthesis tools will determine whether to instantiate a flip-flop based on the usage. Logic is the most commonly used basic data types in SystemVerilog. This can be useful when dealing with x-prorogation.ĭata types that only use 0 or 1 have 2-state values. Any 4-state value OR with 1 is 1, any 4-state value AND with 0 is 0, and any 4-state value XOR with x is x. Notice that the truth table for 4-state values are slightly different than the normal 2-state values. Keep in mind that x can propagate through your circuit if not taken care of, since any logic operation on unknown values results in unknown values. Any signal coming out from the shut-down region will be x. Another common scenario is low-power designs where some part of circuit is “shut-down”, i.e. no supply voltage. One common situation for x to appear in simulation is usage of uninitialized memory cells. Unknown value x means the system is able to determine the value, which may happen in various condition. It commonly appears in designs where a pin used as a bi-directional bus, e.g. tri-state. High-impedance value z typically implies a physically disconnected state, i.e. an infinitely high resistance. Values 0 and 1 serve the same purpose as in languages such as C/C++, but x and z are hardware specific. 1: represents a logic one or true condition.0: represents a logic zero or false condition.One major distinction between SystemVerilog and other software programming languages is that the value set in SystemVerilog consists of the following four basic values: A data object is a named entity that has a data value and a data type associated with it. As specified in the language specification, a data type is a set of values and a set of operations that can be performed on those values. SystemVerilog uses the terminology of data type and data objects to distinguish between objects and its data type. This chapter explores the type system and associated operators in SystemVerilog. Although bears much similarity to languages such as C/C++ (in fact SystemVerilog is influenced by them), SystemVerilog is a language to model hardware, which has different semantics than software programming models. Like ordinary software programming languages, SystemVerilog allows designers manipulate different types and data objects when modeling the hardware.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |